IBM Shrinking CPU Manufacturing Process Using Carbon Nanotubes - PC Magazine

You can currently pick up a CPU that's been designed using a "22 nanometer" process – which is to say, the width of each of the billions of tiny transistors on the chip measures far, far less than the width of a single piece of hair on your head.

That's pretty small. And IBM wants to make it smaller, but perhaps "wants" is the wrong word in this case. It's more like "needs," for while manufacturers are still keen on shrinking their silicon as much as possible, there's growing concern that they're soon going to run out of room. Without some new technological process, the concept of Moore's Law — the notion that the number of transistors on a chip doubles every two years – is going to run out of steam.

IBM's latest research, highlighted today, has scientists replacing silicon transistors with carbon nanotubes to shrink the size of the transistors even further and bump up their speeds compared to their silicon-based counterparts.

"The motivation to work on carbon nanotube transistors is that at extremely small nanoscale dimensions, they outperform transistors made from any other material," said Supratik Guha, Director of Physical Sciences at IBM Research, in a statement. "However, there are challenges to address such as ultra high purity of the carbon nanotubes and deliberate placement at the nanoscale. We have been making significant strides in both."

Manufacturing these wafers presents new challenges, given that one can't simply etch a sheet of carbon nanotubes using a pattern of data pathways as a template. Carbon nanotube-based transistors have to be built from the ground up.

We'll let IBM explain this one:

"The process starts with carbon nanotubes mixed with a surfactant, a kind of soap that makes them soluble in water. A substrate is comprised of two oxides with trenches made of chemically-modified hafnium oxide (HfO2) and the rest of silicon oxide (SiO2). The substrate gets immersed in the carbon nanotube solution and the nanotubes attach via a chemical bond to the HfO2 regions while the rest of the surface remains clean," reads a description on an IBM press release.

In other words, IBM generates a circuit pattern onto a substrate using hafnium oxide and silicon oxide. It then then adheres carbon nanotubes to this pattern creating an attraction between the substance of the substrate's pattern — hafnium oxide — and the solution containing the carbon nanotubes. In doing so, IBM's been able to create a chip with 10,000 of these transistors in place, an improvement from the hundreds or so that researchers were previously able to slap onto a single chip.

So, what's next?

According to VentureBeat's Dean Takahashi, IBM's fabrication technology is at a precision rate of around 99.8 percent. That's good, but not good enough for commercial chip fabrication, which necessitates a precision level of around 99.999 percent – or greater. Additionally, IBM might be able to stick 10,000 carbon nanotube-based transistors on a chip so far, but that number has to successfully bump up to more than one billion before IBM's chips can see the light of day.

Nevertheless, a silver lining awaits those who make use of IBM's research: It's currently compatible with the existing silicon manufacturing process previously described, which will be a boon for current chip factories when it comes time to switch over to this smaller nanometer manufacturing process.

For more tech tidbits from David Murphy, follow him on Facebook or Twitter (@thedavidmurphy).

For the top stories in tech, follow us on Twitter at @PCMag.

');}}
Login or Register blog comments powered by Disqus